Aasemoon.com

FPGAs

From Verse

Altera FPGA





One of my favorite topics... FPGAs... much you can do with these tiny useful things. =)












Contents

eBooks & Articles


pdf_icon.png Architecture of FPGAs and CPLDs Info_circle.png



pdf_icon.png FPGA Technology in Detail Info_circle.png



pdf_icon.png Introduction to Xilinx Virtex FPGA devices tool.pdf‎ Info_circle.png

pdf_icon.png FPGAs "DiSP"lay their processing prowess Info_circle.png

pdf_icon.png Building a High Performance Bit Serial Processor in an FPGA Info_circle.png

pdf_icon.png Modulation and Demodulation Techniques for FPGAs Info_circle.png

pdf_icon.png A Low Complexity Method for Detecting Configuration Upset in SRAM Based FPGAs Info_circle.png

pdf_icon.png FPGAs Make a Radar Signal Processor on a Chip a Reality Info_circle.png


Parameterised automated generation of convolvers implemented in FPGAs

FPGA design from scratch


Refrences & Resources


fpga4fun.com :: Articles, tutorials and tools related to FPGAs.

Simple Interface for Reconfigurable Computing (SIRC) :: This API provides users with a standard FPGA communication interface from C++ code. It is intended to encourage more widespread adoption of FPGAs and reconfigurable computing platforms—particularly among Windows application developers.

Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1)

Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 2)

John's FPGA Page

How to achieve 1 trillion floating-point operations-per-second in an FPGA


Toolbox


Xilinx's ISE WebPACK Design Software :: "ISE® WebPACK™ design software is the industry´s only FREE, fully featured front-to-back FPGA design solution for Linux, Windows XP, and Windows Vista. ISE WebPACK is the ideal downloadable solution for FPGA and CPLD design offering HDL synthesis and simulation, implementation, device fitting, and JTAG programming. ISE WebPACK delivers a complete, front-to-back design flow providing instant access to the ISE features and functionality at no cost. Xilinx has created a solution that allows convenient productivity by providing a design solution that is always up to date with error-free downloading and single file installation."




Lattice Diamond Design Software :: "Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous other enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before."




My FPGA Articles Feed


Power-aware FPGA design (Part 1)12 September 2012

"UBM Electronics "


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Floating Point: Have it Your Way with FPGA Embedded Processors29 July 2012


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WEBENCH® Designer Tools | National Semiconductor31 March 2011


Annotations:



  • With the introduction of the WEBENCH Online Design Environment in 1999, National Semiconductor made it possible for design engineers to create a reliable power supply circuit over the internet in minutes. The user specified the circuit performance and the WEBENCH Toolset delivered. Today, WEBENCH Designer creates and presents all of the possible power, lighting, or sensing circuits that meet a design requirement in seconds. This enables the user to make value based comparisons at a system and supply chain level before a design is committed. This expert analysis is not possible anywhere else.




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DSP options to accelerate your DSP+FPGA design17 October 2010


Annotations:



  • Although signal processing is usually associated with digital signal processors, it is becoming increasingly evident that FPGAs are taking over as the platform of choice in the implementation of high-performance, high-precision signal processing.
     
     For many such applications, the choice generally boils down to using either a single FPGA, a FPGA with an associated DSP processor or a farm of DSP processors.




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Techfocus Media :: Paradox of Pursuit30 September 2010


Annotations:



  • Rube Goldberg couldn’t have designed a more elegant confluence of convoluted causal relationships.  Start analyzing the perplexing paradox of the FPGA synthesis market and each link of the chain reveals a bizarre force vector that eventually doubles back onto itself into an unlikely equilibrium that miraculously has held stable for a full decade despite disruptive forces of epic proportions.

     

    For over a decade now, Synplify has navigated these waters and has continued to survive and thrive through the unlikeliest of conditions.  Now in the hands of EDA giant Synopsys, the Synplify family of FPGA synthesis tools continues to evolve - with a major upgrade this fall. 

     

    When you put a digital design into an FPGA, there are two technologies that determine whether your design fits or doesn’t fit, whether it meets your timing constraints or does not, whether the power consumption will be within your limits (or those of the FPGA), or whether it fails completely, leaving your project at the mercy of major mulligans.   Those two technologies are synthesis and place-and-route. 




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How to achieve timing closure in large, complex FPGA designs26 September 2010


Annotations:



  • This article features an example chapter from a new *Hot-off-the-Press* book on FPGA Design that just recently hit the streets in August 2010. This chapter is reproduced here with the kind permission of the publisher – <a rel="nofollow" target="_blank" href="http://www.springer.com">Springer</a>.
     
     This book -- <a rel="nofollow" target="_blank" href="http://www.springer.com/engineering/circuits+&+systems/book/978-1-4419-6338-3">FPGA Design: Best Practices for Team-Based Design</a> -- describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams.
     
     By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed.




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How to achieve 1 trillion floating-point operations-per-second in an FPGA20 September 2010


Annotations:



  • Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.




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What if Henry Ford was an fpga designer?6 September 2010

Interesting view!


Annotations:



  • Over 100 years ago, when Henry Ford was conceiving a mass produced automobile, it was in an environment where cars were specified and built to order one by one. Each car was 'hand crafted' with the care and precision warranted by a fledgling auto market where society's elite were the only ones who could afford such a revolutionary contraption.




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FPGA compilation on-site or in the cloud23 August 2010


Annotations:



  • It is no secret that field-programmable gate arrays (FPGAs) are getting bigger and more complex all the time. The fabrication process creates smaller transistors and makes more dense chips packing more digital processing per nanometer. Engineers love to see advancement because it means they can do more with modern silicon, and many times NI LabVIEW FPGA Module technology helps by abstracting the complexity to a higher level so that engineers can more smoothly take advantage of these improvements.  Unfortunately, there is one issue with FPGAs that continues to be a time sink and only gets worse with denser FPGAs: compilation time.


  • <a title="FPGA compilation on-site or in the cloud" href="https://www.diigo.com/item/image/2tzu/mwxb"> <img alt="FPGA compilation on-site or in the cloud" src="FPGA+compilation+on-site+or+in+the+cloud.jpg" /> </a>



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Signal processing library speeds up video analytics deployment1 August 2010


Annotations:



  • Pico Computing has developed a <a rel="nofollow" href="http://www.eetasia.com/SEARCH/ART/signal+processing.HTM">signal processing</a> library which is made up of a set of FPGA firmware components and related tools that speed the development and deployment of advanced video and network analytics for security, defense and aerospace applications.

    The library, which includes flexible components for signal analysis, feature detection, scale-space generation, correlation and filtering, has been validated and optimized for Pico Computing platforms based on the latest-generation <a rel="nofollow" title="ASIC prototyping system based on Virtex-4 technology" href="http://www.eetasia.com/ART_8800405461_480100_NP_c454e2e1.HTM">Xilinx Virtex</a>-5 and Virtex-6 FPGA devices.




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FPGAs in next generation wireless networks - Dataweek27 July 2010


Annotations:



  • In addition to voice connectivity, digital cellular wireless networks such as GSM and its enhancement, GSM-EDGE, can now provide increased data speeds up to a (theoretical) limit of 384ᅠKbps.
     Third generation mobile networks, such as CDMA2000 and WCDMA or UMTS (Universal Mobile Telecommunications Standards) and TD-SCDMA (China only) are currently being deployed worldwide. These systems offer services such as video streaming, Internet browsing and, by using a technique called High Speed Packet Access (HSPA), they can in theory deliver downlink speeds up to 14,4 Mbps.


  • <a title="FPGAs in next generation wireless networks - Dataweek" href="https://www.diigo.com/item/image/2tzu/357o"> <img alt="FPGAs in next generation wireless networks - Dataweek" src="FPGAs+in+next+generation+wireless+networks+-+Dataweek.jpg" /> </a>



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Lattice Diamond2 July 2010


Annotations:



  • <img src="img37343.gif" alt="Diamond PR photo" title="" />


  • Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous other enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before.




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Delta-Sigma converters for audio output in an infotainment FPGA22 June 2010


Annotations:



  • Field programmable gate arrays (FPGAs) present an efficient and inexpensive alternative when it comes to implementing complete embedded systems along with important peripheral functions. The reconfigurable logic circuitry of an FPGA offers tremendous flexibility. A lesser known feature is that the outputs of a digital FPGA also permit various analogue applications.


  • <img src="bild1_delta-sigma-dac.png" alt="" title="" />




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Module aids Camera Link FPGA image processing | Industrial Control Designline19 June 2010


Annotations:



  • National Instruments has released a vision module for the PXI platform that provides a high-performance parallel processing architecture for hardware-defined timing, control and image pre-processing.  

     The NI 1483 Camera Link adapter module, in combination with an NI FlexRIO field-programmable gate array (FPGA) board, offers a solution for embedding vision and control algorithms directly on FPGAs which are used to process and analyse an image in real time with little to no CPU intervention. 

     The FPGAs can be used to perform operations by pixel, line and region of interest. They can implement many image processing algorithms that are inherently parallel, including fast Fourier transforms (FFTs), thresholding and filtering.  


  • <img src="2010-06-08_crh_nicamera.jpg" alt="" title="" />




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| Programmable Logic DesignLine18 June 2010


Annotations:



  • Menta SAS and LIRMM have taped out what they believe is the of worlds first MRAM-based FPGA which has patent-protected circuitry enabling compact integration of MRAM and embedded-FPGA solutions. 

     Researchers at the Montpellier Laboratory of Informatics, Robotics and Microelectronics (LIRMM), in France, claimed in <a rel="nofollow" target="_new" href="http://www.pldesignline.com/220300764">October</a> that they had developed a FPGA circuit based on non volatile resistive memory cell. 


  • <img src="2010-06-09_crh_menta2.jpg" alt="" title="" />




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Embedded.com - Protecting FPGAs from power analysis security vulnerabilities1 June 2010


Annotations:



  • Recent advances in the size and performance of FPGAs, coupled with advantages in time-to-market, field-reconfigurability and lower up-front costs, make FPGAs ideally suited to a wide range of commercial and defense applications [6]. In addition, FPGAs generality and reconfigurability provide important protections against the introduction of Trojan horses during semiconductor manufacturing process[8]. As a result, FPGA applications increasingly involve highly-sensitive intellectual property and trade-secrets, as well as cryptographic keys and algorithms [7].


  • <img src="Fig1.jpg" alt="" title="" />




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Embedded.com - Timing Closure on FPGAs7 May 2010


Annotations:



  • Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer version of your tool chain. You review your test bench and verify 100 percent complete test coverage and that all tests have passed with no errors--yet the problem stubbornly remains.

     

      

     While designers understandably place great emphasis on coding and simulation, they often have only a nodding acquaintance with the internal workings of the silicon within an FPGA. As a result, incorrect logic synthesis and timing problems, rather than logic errors, are the cause of most logic failures.

     

      

     But writing FPGA code that creates predictable, reliable logic is simple if designers take the right steps.

     

      

     In FPGA design, logic synthesis and related timing closure occur during compilation. And many things, including I/O cell structure, asynchronous logic and timing constraints, can have a big impact on the compilation process, varying results with each pass through the tool chain. Let's take a closer look at ways to eliminate these variances to better and more quickly achieve timing closure.


  • <img src="fig1_040910.gif" alt="" title="" />




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Leveraging FPGA in PCB system designs | Industrial Control Designline4 May 2010


Annotations:



  • FPGA devices create compelling business drivers generating a tidal wave of FPGA adoption for the implementation of system PCB designs.  

     Obviously, the time to market advantages and capacity/performance characteristics of FPGA devices have delivered on the promise for a viable alternative to more capital resource intensive custom IC/ASIC solutions as well as a successful consolidation vehicle for standard "off the shelf" components in system design creation.




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Samplify introduces ultrasound beamformer IC30 April 2010

Kool!


Annotations:



  • <story> Samplify Systems Inc. (Santa Clara, Calif.) has announced an autofocus beamforming technology for ultrasound imaging. </story>

     The technology uses a 32-channel ultrasound analog front-end receiver module in an ultra-small small-outline dual-in-line configuration based on the SAM1600 family of compressing ADCs.  




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A fork in the road to 28-nm FPGAs | Programmable Logic DesignLine22 April 2010


Annotations:



  • How's this for a wedge issue on a slow news week?

     

     When Xilinx announced earlier this year that it was <a rel="nofollow" href="http://www.eetimes.com/showArticle.jhtml?articleID=223100154">changing one of its foundry suppliers</a> from UMC to TSMC for the 28-nm node, it seemed like a blow to differentiation—at least from a process technology standpoint—between Xilinx and Altera, which has been using TSMC for years.

     

     But while Xilinx chose to go with TSMC's high-performance/low power process, Altera said this week it is going with <a rel="nofollow" href="http://www.eetimes.com/showArticle.jhtml?articleID=224400649">TSMC's high-performance process.</a>

    <a rel="nofollow" href="http://www.eetimes.com/showArticle.jhtml?articleID=224400649"> </a>  

     Altera maintains that customers in the high end communications equipment market are much more concerned about performance than power. Luanne Schirrmeister, senior director of product marketing at Altera, put it this way: "In communications infrastructure, nothing is battery powered. Everything is plugged into a wall."




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